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Signal Processing and Generation Modules

A Comprehensive Guide to Digital Signal Modules

Table of Contents

Introduction

Signal processing and generation are critical components in digital systems, enabling complex waveform creation, analysis, and manipulation. This library provides a comprehensive set of parameterizable modules for various signal-related tasks, from precise waveform generation to signal analysis and random number generation.

Signal Generation

Direct Digital Synthesis (DDS)

Description: A highly configurable Direct Digital Synthesis module for generating sine and cosine waveforms with precise frequency and phase control.

Key Features:

  • Configurable phase and amplitude precision
  • Quarter-sine or full-sine lookup table options
  • Flexible frequency and phase offset control

Principles of Operation:

  • Uses a phase accumulator to generate precise frequencies
  • Implements lookup table-based sine generation
  • Supports quadrant-based optimization for reduced memory usage

Implementation Highlights:

// Phase accumulation and frequency control
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        phase_acc <= {PHASE_WIDTH{1'b0}};
    end else if (enable) begin
        phase_acc <= phase_acc + fcw;  // Frequency Control Word
    end
end

// Sine/Cosine generation using lookup table
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        sine_out <= {OUTPUT_WIDTH{1'b0}};
        cosine_out <= {OUTPUT_WIDTH{1'b0}};
    end else if (enable) begin
        sine_out <= sine_lut[sine_addr];
        cosine_out <= sine_lut[cosine_addr];
    end
end

Applications:

  • Signal generators
  • Communication systems
  • Frequency synthesizers
  • Audio/RF signal generation

Pulse Width Modulation (PWM) Generator

Description: A flexible PWM signal generator with dynamic duty cycle and period control.

Key Features:

  • Configurable counter width
  • Glitch-free duty cycle and period updates
  • Enables precise power control and signal generation

Principles of Operation:

  • Uses a counter to generate PWM signal
  • Updates duty cycle and period synchronously
  • Provides enable and reset controls

Implementation Highlights:

// Counter and PWM output generation
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        counter <= {COUNTER_WIDTH{1'b0}};
        pwm_out <= 1'b0;
    end
    else if (enable) begin
        // Reset counter when period is reached
        if (counter >= period_reg) begin
            counter <= {COUNTER_WIDTH{1'b0}};
        end
        else begin
            counter <= counter + 1'b1;
        end
        
        // Set output based on duty cycle
        pwm_out <= (counter < duty_reg) ? 1'b1 : 1'b0;
    end
end

Applications:

  • Motor control
  • LED dimming
  • Power electronics
  • Analog signal approximation

Multi-Phase PWM Controller

Description: Generates multiple synchronized PWM signals with phase offsets.

Key Features:

  • Supports multiple PWM channels
  • Configurable phase relationships
  • Synchronous updates

Applications:

  • Three-phase motor control
  • Inverter design
  • Complex waveform generation

Signal Analysis

Pulse Width Detector

Description: Monitors and detects pulses exceeding a configurable width threshold.

Key Features:

  • Configurable width counter
  • Edge-triggered detection
  • Prevents counter overflow

Implementation Highlights:

// Pulse width tracking
always @(posedge clk or posedge rst) begin
    if (rst) begin
        counter <= {WIDTH{1'b0}};
        pulse_detected <= 1'b0;
    end else begin
        // Count while signal is high
        if (signal_in) begin
            counter <= (counter == {WIDTH{1'b1}}) ? 
                        counter : counter + 1'b1;
            
            // Check threshold
            if (counter >= threshold) begin
                pulse_detected <= 1'b1;
            end
        end
    end
end

Applications:

  • Signal timing measurement
  • Pulse validation
  • Communication protocol analysis

Random Number Generation

Configurable Linear Feedback Shift Register (LFSR)

Description: A flexible LFSR implementation with configurable tap patterns.

Key Features:

  • Dynamic tap pattern selection
  • Serial and parallel outputs
  • Seed loading capability

Implementation Highlights:

// Configurable feedback generation
generate
    if (WIDTH > 1) begin : multi_bit
        wire [WIDTH-1:0] tapped_bits;
        for (i = 0; i < WIDTH; i = i + 1) begin : tap_gen
            assign tapped_bits[i] = shift_reg[i] & tap_pattern[i];
        end
        
        // XOR reduction for feedback
        always @(*) begin
            xor_result = 1'b0;
            for (j = 0; j < WIDTH; j = j + 1) begin
                xor_result = xor_result ^ tapped_bits[j];
            end
        end
    end
endgenerate

Applications:

  • Pseudo-random number generation
  • Cryptographic systems
  • Testing and simulation
  • Noise generation

LFSR Seed Management

  • External seed input via seed and synchronous load via load_seed
  • Deterministic sequence for a fixed (seed, tap_pattern) pair
  • Choose non-zero seeds to avoid all-zero lock state

Configurable Pseudo-Random Number Generator (PRNG)

Description: A parameterizable PRNG supporting Fibonacci and Galois LFSR modes with reseeding.

Key Features:

  • External seed input seed_in
  • Reseeding control via reseed
  • Non-zero seed enforcement: zero input falls back to parameter SEED
  • Deterministic sequence for fixed (seed, mode, taps)

Implementation Highlights:

// Seed cannot be zero for an LFSR
wire [WIDTH-1:0] actual_seed = (seed_in == {WIDTH{1'b0}}) ? SEED : seed_in;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        lfsr_reg <= SEED;
        valid_reg <= 1'b0;
    end else if (reseed) begin
        lfsr_reg <= actual_seed; // load new seed
        valid_reg <= 1'b0;
    end else if (enable) begin
        lfsr_reg <= next_state;  // Fibonacci or Galois update
        valid_reg <= 1'b1;
    end
end

PRNG Seed Management

  • Provide seeds via seed_in; toggle reseed to load at runtime
  • Zero seeds are replaced by default non-zero SEED
  • Keep (seed, mode, taps) fixed for reproducible sequences

Performance Considerations

Area and Timing Trade-offs

Module Area Complexity Configurability
DDS Medium High Excellent
PWM Generator Low Low Good
Pulse Width Detector Low Low Moderate
LFSR Low Low High

Design Guidelines

  • Use quarter-sine optimization in DDS for reduced memory
  • Select appropriate counter widths for PWM
  • Choose tap patterns carefully for good LFSR randomness

Applications

Embedded Systems

  • Sensor interfaces
  • Motor control
  • Power management

Communication

  • Signal generation
  • Modulation techniques
  • Synchronization

Testing and Simulation

  • Pseudo-random stimulus generation
  • Signal analysis
  • Hardware verification

Implementation Examples

Frequency Synthesis

// DDS for 1 kHz sine wave generation
parameterized_dds #(
    .PHASE_WIDTH(24),
    .OUTPUT_WIDTH(12),
    .LUT_ADDR_WIDTH(10),
    .USE_QUARTER_SINE(1)
) dds_inst (
    .clk(sys_clk),
    .rst_n(reset_n),
    .enable(1'b1),
    .fcw(24'h10000),  // Frequency control word
    .phase_offset(24'b0),
    .sine_out(sine_output),
    .cosine_out(cosine_output)
);

References

  • "Digital Signal Processing" by John G. Proakis
  • "Modern Digital Design" by Richard Zukowski
  • "Embedded System Design" by Peter Marwedel
  • IEEE Transactions on Circuits and Systems
  • "Pseudo-Random Signal Processing" by Theodore S. Rappaport