example.tcl

#!/bin/usr/tclsh

set csv_file openMSP430_design_details.csv

package require csv
package require struct::matrix 

struct::matrix m


set f [open $csv_file r]
csv::read2matrix $f m , auto

close $f

set columns [m columns]
set rows [m rows]

#puts $columns
#puts $rows

m link my_arr

set i 0

while {$i < $rows} {

	#puts "setting $my_arr(0,$i) as $my_arr(1,$i)"

	if {$i==0} {
		set [string map {" " ""} $my_arr(0,$i)] $my_arr(1,$i)
	} else {
		set [string map {" " ""} $my_arr(0,$i)] [file normalize $my_arr(1,$i)]
	}
        set i [expr {$i+1}]
}
puts "Design Name        =$DesignName"
puts "output directory   =$OutputDirectory"
puts "netlist directory  =$NetlistDirectory"
puts "constranints file  =$ConstraintsFile"
puts "ealry library path =$EarlyLibraryPath"
puts "late library path  =$LateLibraryPath"

struct::matrix cons
set c [open $ConstraintsFile r]
csv::read2matrix $c cons , auto

close $c

set columnsc [cons columns]
set rowsc    [cons rows]

#puts $columnsc
#puts $rowsc


#finding the row and column number for constraints

set clk_start [lindex [lindex [cons search all CLOCKS] 0] 1]
#puts $clk_start

set clk_start_col [lindex [lindex [cons search all CLOCKS] 0] 0]
#puts $clk_start_col

set ip_start [lindex [lindex [cons search all INPUTS] 0] 1]
#puts $ip_start

set op_start [lindex [lindex [cons search all OUTPUTS] 0] 1]
#puts $op_start

#set clk_start1 [lindex [lindex [cons search all early_rise_delay] 0] 0]
#puts "clock start value using search all command = $clk_start1"

set clk_erd_start [lindex [lindex [cons search rect $clk_start_col $clk_start [expr {$columnsc-1}] [expr {$ip_start-1}] early_rise_delay] 0] 0] 
#puts "$clk_erd_start"
set clk_efd_start [lindex [lindex [cons search rect $clk_start_col $clk_start [expr {$columnsc-1}] [expr {$ip_start-1}] early_fall_delay] 0] 0]
#puts "$clk_efd_start"
set clk_lrd_start [lindex [lindex [cons search rect $clk_start_col $clk_start [expr {$columnsc-1}] [expr {$ip_start-1}] late_rise_delay] 0] 0]
#puts "$clk_lrd_start"
set clk_lfd_start [lindex [lindex [cons search rect $clk_start_col $clk_start [expr {$columnsc-1}] [expr {$ip_start-1}] late_fall_delay] 0] 0]
#puts "$clk_lfd_start"

set clk_ers_start [lindex [lindex [cons search rect $clk_start_col $clk_start [expr {$columnsc-1}] [expr {$ip_start-1}] early_rise_slew] 0] 0]
#puts "$clk_ers_start"
set clk_efs_start [lindex [lindex [cons search rect $clk_start_col $clk_start [expr {$columnsc-1}] [expr {$ip_start-1}] early_fall_slew] 0] 0]
#puts "$clk_efs_start"
set clk_lrs_start [lindex [lindex [cons search rect $clk_start_col $clk_start [expr {$columnsc-1}] [expr {$ip_start-1}] late_rise_slew] 0] 0]
#puts "$clk_lrs_start"
set clk_lfs_start [lindex [lindex [cons search rect $clk_start_col $clk_start [expr {$columnsc-1}] [expr {$ip_start-1}] late_fall_slew] 0] 0]
#puts "$clk_lfs_start"


set clk_freq_start [lindex [lindex [cons search all frequency] 0] 0]
#puts "$clk_freq_start"
set clk_dutycycle_start [lindex [lindex [cons search all duty_cycle] 0] 0]
#puts "$clk_dutycycle_start"

# Creating an SDC file and writing constraints into it

set sdc_file [open $OutputDirectory/examp/$DesignName.sdc "w"]

set i [expr {$clk_start+1}]
set eoc [expr {$ip_start-1}]

while {$i < $eoc} {
	puts -nonewline $sdc_file "\ncreate_clock -name [cons get cell 0 $i] -period [cons get cell 1 $i] -waveform \{0 [expr {[cons get cell 1 $i]*[cons get cell 2 $i]/100}] \} \[get_ports [cons get cell 0 $i]\]"
	puts -nonewline $sdc_file "\nset_clock_transition -min -rise [cons get cell $clk_ers_start $i] \[get_clocks [cons get cell 0 $i]\]"
	puts -nonewline $sdc_file "\nset_clock_transition -min -fall [cons get cell $clk_efs_start $i] \[get_clocks [cons get cell 0 $i]\]"
	puts -nonewline $sdc_file "\nset_clock_transition -max -rise [cons get cell $clk_lrs_start $i] \[get_clocks [cons get cell 0 $i]\]"
	puts -nonewline $sdc_file "\nset_clock_transition -max -fall [cons get cell $clk_lfs_start $i] \[get_clocks [cons get cell 0 $i]\]"

	puts -nonewline $sdc_file "\nset_clock_latency -min -rise [cons get cell $clk_erd_start $i] \[get_clocks [cons get cell 0 $i]\]"
        puts -nonewline $sdc_file "\nset_clock_latency -min -fall [cons get cell $clk_efd_start $i] \[get_clocks [cons get cell 0 $i]\]"
	puts -nonewline $sdc_file "\nset_clock_latency -max -rise [cons get cell $clk_lrd_start $i] \[get_clocks [cons get cell 0 $i]\]"
        puts -nonewline $sdc_file "\nset_clock_latency -max -fall [cons get cell $clk_lfd_start $i] \[get_clocks [cons get cell 0 $i]\]"

	set i [expr {$i+1}]
}

#input section - printing input port constraint values to the SDC file

set ip_erd_start [lindex [lindex [cons search rect $clk_start_col $ip_start [expr {$columnsc-1}] [expr {$op_start-1}] early_rise_delay] 0] 0]
#puts "$ip_erd_start"
set ip_efd_start [lindex [lindex [cons search rect $clk_start_col $ip_start [expr {$columnsc-1}] [expr {$op_start-1}] early_fall_delay] 0] 0]
#puts "$ip_efd_start"
set ip_lrd_start [lindex [lindex [cons search rect $clk_start_col $ip_start [expr {$columnsc-1}] [expr {$op_start-1}] late_rise_delay] 0] 0]
#puts "$ip_lrd_start"
set ip_lfd_start [lindex [lindex [cons search rect $clk_start_col $ip_start [expr {$columnsc-1}] [expr {$op_start-1}] late_fall_delay] 0] 0]
#puts "$ip_lfd_start"

set ip_ers_start [lindex [lindex [cons search rect $clk_start_col $ip_start [expr {$columnsc-1}] [expr {$op_start-1}] early_rise_slew] 0] 0]
#puts "$ip_ers_start"
set ip_efs_start [lindex [lindex [cons search rect $clk_start_col $ip_start [expr {$columnsc-1}] [expr {$op_start-1}] early_fall_slew] 0] 0]
#puts "$ip_efs_start"
set ip_lrs_start [lindex [lindex [cons search rect $clk_start_col $ip_start [expr {$columnsc-1}] [expr {$op_start-1}] late_rise_slew] 0] 0]
#puts "$ip_lrs_start"
set ip_lfs_start [lindex [lindex [cons search rect $clk_start_col $ip_start [expr {$columnsc-1}] [expr {$op_start-1}] late_fall_slew] 0] 0]
#puts "$ip_lfs_start"

set ip_related_clock [lindex [lindex [cons search rect $clk_start_col $ip_start [expr {$columnsc-1}] [expr {$op_start-1}] clocks] 0] 0]



set i [expr {$ip_start+1}]

set eoi [expr {$op_start-1}]

while { $i < $eoi } {
	set netlist [glob -dir $NetlistDirectory *.v]
	set tmp_file [open /tmp/1 w]
	foreach f $netlist {
		set fd [open $f]
		while { [gets $fd line] != -1} {
			set pattern1 " [cons get cell 0 $i];"
			#puts $pattern1
			if { [regexp -all -- $pattern1 $line] } {
				set pattern2 [lindex [split $line ";"]0]
				#puts $pattern2
				if { [regexp -all {input} [lindex [split $pattern2 "\S+"] 0] ] } {
					set s1 "[lindex [split $pattern2 "\S+"] 0] [lindex [split $pattern2 "\S+"] 1] [lindex [split $pattern2 "\S+"] 2]"
					puts -nonewline $tmp_file "\n[regsub -all {\s+} $s1 " "]"
				}
			}
		}
		close $fd
	}
	close $tmp_file
	set tmp_file [open /tmp/1 r]
	set tmp2_file [open /tmp/2 w]
	puts -nonewline $tmp2_file "[join [lsort -unique [split [read $tmp_file] \n]] \n]"
	close $tmp_file
	close $tmp2_file
	set tmp2_file [open /tmp/2 r]
	set count [llength [split [read $tmp2_file] \n]]
	close $tmp2_file
	if {$count > 2} {
		set ip_ports [concat [cons get cell 0 $i]*]
	} else {
		set ip_ports [cons get cell 0 $i]
	}


	puts -nonewline $sdc_file "\nset_input_transition -clock \[get_clocks [cons get cell $ip_related_clock $i]\] -min -rise -source_lateny_included [cons get cell $ip_ers_start $i] \[get_ports $ip_ports\]"
	puts -nonewline $sdc_file "\nset_input_transition -clock \[get_clocks [cons get cell $ip_related_clock $i]\] -min -fall -source_lateny_included [cons get cell $ip_efs_start $i] \[get_ports $ip_ports\]"
	puts -nonewline $sdc_file "\nset_input_transition -clock \[get_clocks [cons get cell $ip_related_clock $i]\] -max -rise -source_lateny_included [cons get cell $ip_lrs_start $i] \[get_ports $ip_ports\]"
	puts -nonewline $sdc_file "\nset_input_transition -clock \[get_clocks [cons get cell $ip_related_clock $i]\] -max -fall -source_lateny_included [cons get cell $ip_lfs_start $i] \[get_ports $ip_ports\]"


	puts -nonewline $sdc_file "\nset_input_delay -clock \[get_clocks [cons get cell $ip_related_clock $i]\] -min -rise -source_lateny_included [cons get cell $ip_erd_start $i] \[get_ports $ip_ports\]"
        puts -nonewline $sdc_file "\nset_input_delay -clock \[get_clocks [cons get cell $ip_related_clock $i]\] -min -fall -source_lateny_included [cons get cell $ip_efd_start $i] \[get_ports $ip_ports\]"
        puts -nonewline $sdc_file "\nset_input_delay -clock \[get_clocks [cons get cell $ip_related_clock $i]\] -max -rise -source_lateny_included [cons get cell $ip_lrd_start $i] \[get_ports $ip_ports\]"
        puts -nonewline $sdc_file "\nset_input_delay -clock \[get_clocks [cons get cell $ip_related_clock $i]\] -max -fall -source_lateny_included [cons get cell $ip_lfd_start $i] \[get_ports $ip_ports\]"
	set i [expr {$i+1}]
}


#Output Section - Printing output ports constraint values to the SDC file

set op_erd_start [lindex [lindex [cons search rect $clk_start_col $op_start [expr {$columnsc -1}] [expr {$rowsc -1}] early_rise_delay] 0] 0]
set op_efd_start [lindex [lindex [cons search rect $clk_start_col $op_start [expr {$columnsc -1}] [expr {$rowsc -1}] early_fall_delay] 0] 0]
set op_lrd_start [lindex [lindex [cons search rect $clk_start_col $op_start [expr {$columnsc -1}] [expr {$rowsc -1}] late_rise_delay] 0] 0]
set op_lfd_start [lindex [lindex [cons search rect $clk_start_col $op_start [expr {$columnsc -1}] [expr {$rowsc -1}] late_fall_delay] 0] 0]


#puts "$op_erd_start"
#puts "$op_efd_start"
#puts "$op_lrd_start"
#puts "$op_lfd_start"

set op_related_clock [lindex [lindex [cons search rect $clk_start_col $op_start [expr {$columnsc -1}] [expr {$rowsc -1}] clocks] 0] 0]

set op_load_start [lindex [lindex [cons search rect $clk_start_col $op_start [expr {$columnsc -1}] [expr {$rowsc -1}] load] 0] 0]

#puts "$op_related_clock"
#puts "$op_load_start"

set i [expr {$op_start+1}]
set eoo [expr {$rowsc-1}]

while {$i < $eoo} {
	set netlist [glob -dir $NetlistDirectory *.v]
        set tmp_file [open /tmp/1 w]
        foreach f $netlist {
                set fd [open $f]
                while { [gets $fd line] != -1} {
                        set pattern1 " [cons get cell 0 $i];"
                        #puts $pattern1
                        if { [regexp -all -- $pattern1 $line] } {
                                set pattern2 [lindex [split $line ";"]0]
                                #puts $pattern2
                                if { [regexp -all {output} [lindex [split $pattern2 "\S+"] 0] ] } {
                                        set s1 "[lindex [split $pattern2 "\S+"] 0] [lindex [split $pattern2 "\S+"] 1] [lindex [split $pattern2 "\S+"] 2]"
                                        puts -nonewline $tmp_file "\n[regsub -all {\s+} $s1 " "]"
                                }
                        }
                }
                close $fd
        }
        close $tmp_file
        set tmp_file [open /tmp/1 r]
        set tmp2_file [open /tmp/2 w]
        puts -nonewline $tmp2_file "[join [lsort -unique [split [read $tmp_file] \n]] \n]"
        close $tmp_file
        close $tmp2_file
        set tmp2_file [open /tmp/2 r]
        set count [llength [split [read $tmp2_file] \n ] ]
        close $tmp2_file
        if {$count > 2} {
                set op_ports [concat [cons get cell 0 $i]*]
        } else {
                set op_ports [cons get cell 0 $i]
        }


        puts -nonewline $sdc_file "\nset_output_delay -clock \[get_clocks [cons get cell $op_related_clock $i]\] -min -rise -source_lateny_included [cons get cell $op_erd_start $i] \[get_ports $op_ports\]"
	puts -nonewline $sdc_file "\nset_output_delay -clock \[get_clocks [cons get cell $op_related_clock $i]\] -min -fall -source_lateny_included [cons get cell $op_erd_start $i] \[get_ports $op_ports\]"
	puts -nonewline $sdc_file "\nset_output_delay -clock \[get_clocks [cons get cell $op_related_clock $i]\] -max -rise -source_lateny_included [cons get cell $op_erd_start $i] \[get_ports $op_ports\]"
	puts -nonewline $sdc_file "\nset_output_delay -clock \[get_clocks [cons get cell $op_related_clock $i]\] -max -fall -source_lateny_included [cons get cell $op_erd_start $i] \[get_ports $op_ports\]"
	puts -nonewline $sdc_file "\nset_load [cons get cell $op_load_start $i]\] \[get_ports $op_ports\]"


	set i [expr {$i+1}]
}

close $sdc_file

#Constrant file generation completed. Can be found by the name OpenMSP430.sdc


#Heirarchy check


puts "Creating heirarchy script to be used by yosys"
set data "read_liberty -lib -ignore_miss_dir -setattr blackbox ${LateLibraryPath}"
set filename "$DesignName.hier.ys"
set fileId [open $OutputDirectory/examp/$filename "w"]
puts -nonewline $fileId $data
set  netlist [glob -dir $NetlistDirectory *.v]
foreach f $netlist {
	puts -nonewline $fileId "\nread_verilog $f"
}
puts -nonewline $fileId "\nhierarchy -check"
close $fileId

#Running hierarchy check in yosys and dumpping the log file

set error_flag [catch { exec yosys -s $OutputDirectory/examp/$DesignName.hier.ys >& $OutputDirectory/examp/$DesignName.hierarchy_check.log} msg]
puts "Started using synthesis tool yosys"
if {$error_flag} {
	set filename "$OutputDirectory/examp/$DesignName.hierarchy_check.log"
	set pattern {referenced in module}
	set count 0
	set fid [open $filename r]
	while { [gets $fid line] != -1} {
		incr count [regexp -all -- $pattern $line]
		if { [regexp -all -- $pattern $line] } {
			puts "\nError: Module [lindex $line 2] is not a part of $DesignName"
			puts "Hierarchy check failed"
		}
	}
	close $fid
	puts "\nInfo: check hierarchy details at '[file normalize $OutputDirectory/examp/$DesignName.hierarchy_check.log]'"
	exit
} else {
	puts "\nInfo: Hierarchy check PASS"
	puts "\nInfo: check hierarchy details at '[file normalize $OutputDirectory/examp/$DesignName.hierarchy_check.log]'" 
}

	
#Synthesis script generation

puts "\nCreating main synthesis script to be used by yosys"
set data "read_liberty -lib -ignore_miss_dir -setattr blackbox ${LateLibraryPath}"
set filename "$DesignName.ys"
set fileId [open $OutputDirectory/examp/$DesignName.ys "w"]
puts -nonewline $fileId $data
set netlist [glob -dir $NetlistDirectory *.v]
foreach f $netlist {
	puts -nonewline $fileId "\nread_verilog $f"
}
puts -nonewline $fileId "\nhierarchy -top $DesignName"
puts -nonewline $fileId "\nsynth -top $DesignName"
puts -nonewline $fileId "\nsplitnets -ports -format __\ndfflibmap -liberty ${LateLibraryPath} \nopt"
puts -nonewline $fileId "\nabc -liberty ${LateLibraryPath}"
puts -nonewline $fileId "\nflatten"
puts -nonewline $fileId "\nclean -purge\niopadmap -outpad BUFX2 A:Y -bits\nopt\nclean"
puts -nonewline $fileId "\nwrite_verilog $OutputDirectory/examp/$DesignName.synth.v"
close $fileId
puts "\nInfo: Synthesis script generated at $OutputDirectory/examp/$DesignName.ys"

#Running synthesis and catching any errors

if [catch {exec yosys -s $OutputDirectory/examp/$DesignName.ys >& $OutputDirectory/examp/$DesignName.synthesis.log} msg] {
	puts "\nError: Syntheis failed due to errors"
	exit
} else {
	puts "\nSynthesis finished successfully and log file can be found at $OutputDirectory/examp/$DesignName.syntesis.log"
}

#Editing synth.v file in a format compatible for opentimer

set fileId [open /tmp/1 "w"]

puts -nonewline $fileId [exec grep -v -w "*" $OutputDirectory/examp/$DesignName.synth.v]
close $fileId
set output [open $OutputDirectory/examp/$DesignName.final.synth.v "w"]
set filename "/tmp/1"
set fid [open $filename r]

while { [gets $fid line] != -1} {
	puts -nonewline $output [string map {"//" ""} $line]
	puts -nonewline $output "\n"
}
close $fid
close $output

puts "\nInfo: Final Synthesized netlist to be used for STA and PNR is generated at $OutputDirectory/examp/$DesignName.final.synth.v."


#Timing analysis started 
puts "\nInfo: Initialising number of threads, libraries, sdc, verilog netlist, netlist path...."
puts "\nInfo: Sourcing required PROC's used in Timing Analysis"

source /home/vsduser/vsdsynth/procs/reopenStdout.proc
source /home/vsduser/vsdsynth/procs/set_multi_cpu_usage.proc
source /home/vsduser/vsdsynth/procs/read_verilog.proc
source /home/vsduser/vsdsynth/procs/read_lib.proc
source /home/vsduser/vsdsynth/procs/read_sdc.proc

reopenStdout $OutputDirectory/examp/$DesignName.conf
set_multi_cpu_usage -localCpu 4
read_lib -early $EarlyLibraryPath
read_lib -late $LateLibraryPath
read_verilog $OutputDirectory/examp/$DesignName.final.synth.v
read_sdc $OutputDirectory/examp/$DesignName.sdc
reopenStdout /dev/tty

#Writing SPEF

set enable_prelayout_timing 1
puts "\nInfo: setting enable_prelayout_timing as $enable_prelayout_timing to write default .spef values with zero-wire load parasitics since, actual .spef will be  avaliable after routing."
if {$enable_prelayout_timing ==1} {
	puts "\nInfo: Enabling zero-wire load parasitics"
	set spef_file [open $OutputDirectory/examp/$DesignName.spef "w"]
	puts $spef_file "*SPEF \"IEEE 1481-1998\" "
	puts $spef_file "*DESIGN \"$DesignName\" "
	puts $spef_file "*DATE \"[clock format [clock seconds] -format {%a %b %d %I:%M:%S %Y}]\" "
	puts $spef_file "*VENDOR \"TAU 2015 Contest\" "
	puts $spef_file "*PROGRAM \"Benchmark Parasitic Generator\" "
	puts $spef_file "*VERSION \"0.0\" "
	puts $spef_file "*DESIGN_FLOW \"NETLIST_TYPE_VERILOG\" "
	puts $spef_file "*DIVIDER / "
	puts $spef_file "*DELIMITER : "
	puts $spef_file "*BUS_DELIMITER \[ \] "
	puts $spef_file "*T_UNIT 1 PS "
	puts $spef_file "*C_UNIT 1 FF "
	puts $spef_file "*R_UNIT 1 KOHM "
	puts $spef_file "*L_UNIT 1 UH "
	close $spef_file
}

#Appending to a .conf file

puts "\nInfo:Appending rest of the commands to the .conf file"
set conf_file [open $OutputDirectory/examp/$DesignName.conf a]
puts $conf_file "set_spef_fpath $OutputDirectory/examp/$DesignName.spef"
puts $conf_file "init_timer"
puts $conf_file "report_timer"
puts $conf_file "report_wns"
puts $conf_file "report_worst_paths -numPaths 10000"
close $conf_file

puts "\nEnterning STA analysis using OpenTimer tool"

#Static Timing Analysis using OpenTimer

set tcl_precision 3
set time_elapsed_in_us [time {exec /home/vsduser/OpenTimer-1.0.5/bin/OpenTimer < $OutputDirectory/examp/$DesignName.conf >& $OutputDirectory/examp/$DesignName.results}]
set time_elapsed_in_sec "[expr {[lindex $time_elapsed_in_us 0]/1000000.0}]sec"
puts "\nInfo:STA finished in $time_elapsed_in_sec seconds"
puts "\nInfo:Refer to $OutputDirectory/examp/$DesignName.results for warnings and errors"