PCB: PanelGroup base Rev 2 — adopt the 74HC ShiftBus pin standard

[mottihoresh]

Current truth (supersedes the early comments): Rev 1 (ordered JLCPCB, June 2026) predates the #197 backend decision and is NOT hardware-SPI as fabbed — PB3/PB4 are left NC, so there is no SCK/MISO and no shift-register connector. (The base-boards.md "breakout (JTAG remap)" row describes a planned state, not the fabbed board — a doc-drift item fixed here.) Bench-bridge a 74HC node on Rev 1 by jumpering SR_SCK/SR_MISO off the socketed module's PB3/PB4 pins, or via a parked soft-SPI fallback. Rev 2 remap is required for production 74HC nodes.

Rev 2 bakes the ShiftBus standard in. Spec: the 2026-07-02 comment on #95; firmware standard in #207 (ShiftBus.md TechSpec).

Two halves

• Design — pin remap + J_SR connector + base-boards.md fix. This is the reusable ShiftBus pinout; it gates any board that inherits the PanelGroup base (e.g. a host-integrated controller board copies this pinout as its design block). Low-risk, mostly mechanical (applying the already-decided feat(PanelGroup): ShiftBus — 74HC165/74HC595 SPI shift-register PinRef backend #207 standard).
• Fab — order + bring-up. Trails the design half; batched with Rev-1 bring-up findings (below). A comfort/production revision, not a bench blocker (Rev 1 serves via the jumper bridge).

Scope — design

• Schematic pin remap: PB3=SR_SCK · PB4=SR_MISO · PB5=SR_MOSI (SPI1-remap) · PB8=SR_LOAD · PB9=SR_LATCH; MCP INT lines move to PB12/PB13
• New J_SR connector: SCK · MOSI · MISO · LOAD · LATCH · +3V3 · GND (matches the corrected J_SPI1 spec on Controller: Right_Navigation #168)
• J3 breakout + pin-table rows reconciled (status LEDs PB14/PB15 and I2C1/I2C2 unaffected; SPI2 deliberately not reserved)
• docs/_source/base-boards.md — PanelGroup-base pin tables + connector list corrected (fix the planned-vs-fabbed PB3/PB4 drift, add J_SR)
• ERC 0 / DRC 0, gerbers exported (gitignored), BOM delta vs Rev 1

Scope — fab

• Sequencing: hold the Rev 2 order until Rev 1 bring-up validates the non-SPI subsystems — I2C1/I2C2 (4.7 k pull-ups + series legs), status LEDs (PB14/PB15), DiagSerial, backlight PWM zones (PA6/PA7 → Q2/Q3), power circuits. Fold any findings into Rev 2.
• Order Rev 2 from JLCPCB
• Bring-up: flash Firmware/Tests/ShiftBus bench envs through J_SR; optionally the sustained 2-chip cascade run deferred from feat(PanelGroup): investigate 74HC165 shift-register input backend (SPI PISO) for all-input panels #197 (breadboard contact was the blocker, traces should settle it)

Rev 1 disposition (resolved)

• Rev 1 is not hw-SPI as fabbed (PB3/PB4 NC). Bench options: (1) jumper SCK/MISO off the socketed module's PB3/PB4 header pins; (2) parked soft-SPI (SHIFTBUS_SOFT) backend — viable, not implemented. PB8/PB9 reach the J_I2C2 INT pins (6/7) through 100 Ω series — in-spec for the LOAD/LATCH strobes.

Implementation detail (build-ready spec — from #207)

Rev-1 → Rev-2 pin changes (5 pins; PanelGroup base table in base-boards.md):

Pin	Rev-1 (as-built)	Rev-2	Note
PB3 (39)	breakout / NC (JTAG)	SR_SCK	SPI1 remap
PB4 (40)	breakout / NC (JTAG)	SR_MISO	SPI1 remap
PB5 (41)	breakout GPIO	SR_MOSI	SPI1 remap
PB8 (45)	I2C2 INT_A → J_I2C2.6	SR_LOAD	strobe
PB9 (46)	I2C2 INT_B → J_I2C2.7	SR_LATCH	strobe

Unchanged: PB12/PB13 = I2C1 INT_A/B (already there — "MCP INT moves to PB12/PB13" was imprecise, they were always here); PA6/PA7 backlight; PB6/PB7 I2C1; PB10/PB11 I2C2.

Real semantic change: I2C2 loses its INT lines → becomes an INT-less display/output-only bus (OLED / output expanders). Only I2C1 keeps INT-driven MCP (PB12/PB13). One INT-MCP bus, not two — matches the #198/#207 model.

3 connector decisions (drawing choices):

1. New J_SR — 7-pin: SCK · MOSI · MISO · LOAD · LATCH · +3V3 · GND (per Controller: Right_Navigation #168 J_SPI1 spec).
2. J_I2C2 pins 6/7 (old INT_A/B) freed — keep the 8-pin header with 6/7 as NC/spare (uniform with J_I2C1), or shrink to 4-pin. Recommend keep-8 + mark NC.
3. Strobe series-R — PB8/PB9 had 100 Ω (INT series). Keep 100 Ω (in-spec) or drop to 33 Ω remote-leg practice for LOAD/LATCH.

Layout hint (#207): bus pins (PB3,4,5,8,9) + I2C1 (PB6,7) = one contiguous run PB3–PB9 → place J_SR adjacent to J_I2C1, group the run for cleaner routing.

SPI1 remap (PB3/4/5) needs AFIO SPI1-remap + JTAG-disable — already required for the JTAG-remap breakout; SWD on PA13/PA14 unaffected.

Parent lifecycle: #95 (stays open through fab → bring-up → docs). Related: #96 (base-board design PR), #197/#133 (decision + gates), #207 (firmware), #208 (standards docs), #168 (Right_Nav consumes the standard).

---

Finding parked for this revision — VDDA filtering is partial (2026-08-14, corrected)

Not actionable on Rev 1 (already fabbed); noted here so it is considered before Rev 2 layout.

Correction to an earlier version of this note, which claimed VDDA was unfiltered. It is not —
base-boards-combined-order-bom.csv carries a 1uF 0805 X7R explicitly annotated "VDDA filter".
The earlier claim came from grepping the schematic for a VDDA net and finding only a symbol pin
name, which was the wrong check. Read the BOM, not the net names.

What is actually absent:

• No ferrite / inductor anywhere in the BOM. So VDDA has a decoupling capacitor, not an LC
  filter. ST's guidance for the F103 is a ferrite bead plus 100 nF and 1 uF; we have the capacitor
  half. Worth deciding whether the bead is warranted — VDDA is the ADC's voltage reference, 3.3 V
  comes from an AMS1117 fed by a switching 5 V rail, and LDO PSRR rolls off well before the
  ~65-100 kHz an ATX supply switches at.

• No RC at the analog inputs — and that is deliberate, not a gap. The base-board design record
  states it explicitly: "Per-channel ADC RC filter (1k+100nF) added per variant." The generic base
  cannot know what is wired to it, so the filter belongs on the variant board. Recorded here only
  because it is easy to misread the BOM's absence as an oversight — it is a decision.

  Worth carrying into any variant that takes an analog axis: the capacitor must be at the MCU
  end, not the panel end. Beyond anti-aliasing it acts as the charge reservoir for the
  sample-and-hold, and fix(firmware): ADC prescaler never configured — ADCCLK runs at 36 MHz against a 14 MHz maximum #263 showed that to be load-bearing — acquisition time scales with the ADC
  clock, and under-settled sampling cost ~3x on measured span. A series R at the sensor end does a
  different job (isolating the sensor's output amplifier from cable capacitance); it does not
  substitute.

Interpretation note for Rev 1 measurements: when characterising analog noise on the assembled
Rev 1 (see #263, #261), neither of the above is present, so it is not the final noise floor —
though it should still be a large improvement over the breadboard, whose contact resistance
dominated everything.

Not a filtering issue, recorded to avoid re-litigating it: the ceramic -> electrolytic swap
(PR #235) is the AMS1117's input and output bulk. The output electrolytic is arguably required
rather than merely cheaper — that regulator family needs a minimum ESR for loop stability, and an
all-ceramic output can oscillate. HF decoupling is still handled by the 100 nF ceramics.

[mottihoresh]

Rev 1 disposition — resolved (doc check, 2026-07-02): Rev 1 IS ShiftBus-capable as-built. All five standard pins are accessible: PB3/PB4/PB5 on the breakout header (JTAG-remap pins — firmware releases JTAG), PB8→J_I2C2.6 and PB9→J_I2C2.7 (routed as INT_A/INT_B through 100 Ω series — within spec for the strobes; remote-leg practice is 33 Ω). Zero firmware changes — standard ShiftBus1 pins. Trade: J_I2C2's INT pins are consumed (74HC nodes don't use MCP INTs; I2C2 SDA/SCL stay free for OLEDs), and LOAD/LATCH ride the I2C connector instead of a dedicated J_SR.

Consequence: Rev 2 is a comfort/ergonomics revision, not a blocker — Rev 1 boards serve 74HC controllers now; batch Rev 2 with the next design change.

[mottihoresh]

Correction to the previous comment — Rev 1 is NOT hardware-SPI capable as fabbed. The actual Rev 1 schematic shows PB3 (39) and PB4 (40) NC (X'd) — the base-boards.md pin table row claiming "breakout (JTAG remap)" for the PanelGroup base describes a planned state, not the fabbed board (doc-drift item: fix the table alongside this Rev). PB5/PB8/PB9 are reachable, but without SCK/MISO there is no hardware ShiftBus through Rev 1 connectors.

Rev 1 bridge options while Rev 2 is pending:

1. If the STM32 module is socketed, jumper SR_SCK/SR_MISO directly off the module's PB3/PB4 header pins — bench-grade.
2. Possible firmware fallback: soft-SPI (bit-bang) ShiftBus backend on free breakout GPIOs (~100–300 kHz, still ample for loop-rate + 1 kHz ISR) — would make Rev 1 serviceable through proper connectors; not yet implemented.

Rev 2 is therefore back to being required for production 74HC nodes, per the original scope above.

[mottihoresh]

Sequencing decision: Rev 2 order waits until Rev 1 bring-up validates the non-SPI subsystems — I2C1/I2C2 (incl. the 4.7 k pull-ups + 33 Ω series legs), status LEDs (PB14/PB15), DiagSerial, backlight PWM zones (PA6/PA7 → Q2/Q3), and the power circuits. Anything found there folds into Rev 2 alongside the ShiftBus pin adoption.

Soft-SPI (SHIFTBUS_SOFT) fallback: parked, not implemented — viable if Rev 1 ever needs to host a 74HC node (J_I2C2 pins 1/2/6/7 + PB5 breakout; series 33/100 Ω are in-spec, populate don't omit), but current plan doesn't need it.