| Revision | Release Summary |
|---|---|
| 2016.01 | Added the inclusion of the PCIe C model to CoSim library compilation |
| Changes in support of PCIe VC | |
| Added VIrq CoSim procedure | |
| Updated rv32 RISC-V ISS to v1.3.1 | |
| 2024.07 | Updated calls to CreateClock for it being moved to ClockResetPkg |
| 2023.?? | Updates to RISC-V ISS libraries and headers for FreeRTOS support |
| 2023.05 | Support for split transactions, responder, streaming and checking |
| 2023.01 | Initial release |
- Added the inclusion of the PCIe C model to CoSim library compilation.
These new libraries exits in
PCIe/lib, with headers inPCIe/include - Changes in support of PCIe VC, including adding support for
SetModelOptionsandGetModelOptions - Added a
VIrqco-simulation procedure, wrapped in a newCoSimIrqVHDL procedure, to raise interrupts independent ofCoSimTranswhere required - The rv32 RISC-V instruction set simulator library is updated to verion 1.3.1. New features include:
- API access to internal cycle count
- Registering of callback function on unimplemented instruction
- Internal timing model configurable over API
- Generation of software interrupt over external IRQ callback
- Support for RV32B standard extensions (Zba, Zbb and Zbs)
- Support for RV32_Zbc standard extension
- Reading of binary program in addition to ELF support
- Updated calls to CreateClock for it being moved to ClockResetPkg
- Updates RISC-V ISS rv32 libraries and include headers for new features and fixes to support running FreeRTOS real-time operating system
- Added split transaction methods for address bus model independent manager
- Added support address bus model independent subordinate/responder
- Added support for streaming bus model independent transactions
- Added test data pattren generation methods
- Added data check methods
- New repository with ability to run C code in the testbench in a CoSim environment. See README.md
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