Skip to content

Commit 78d4d41

Browse files
committed
Update CHANGELOG
1 parent 4861044 commit 78d4d41

1 file changed

Lines changed: 1 addition & 0 deletions

File tree

CHANGELOG.md

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -59,6 +59,7 @@
5959
- Remove data copying between system and components in `PowerElectronics` models.
6060
- Added multi-contingency analysis application.
6161
- Added `BusToSignalAdapter` component for communicating bus voltages and injection currents.
62+
- Added `REGCA` converter model implementation for PhasorDynamics.
6263

6364
## v0.1
6465

0 commit comments

Comments
 (0)