Merge branch 'bump-rocket' into 'master'

Bump rocket

See merge request pard/labeled-RISC-V!230

Author: Wonicon

.gitignore

@@ -10,3 +10,14 @@ ControlPlanes.v
 src/main/scala/.idea/
 src/main/scala/build.sbt
 src/main/scala/project/
+
+.idea/
+boom-ether.err
+bootrom/bootrom.txt
+emulator/boom-failed.md
+emulator/log.txt
+emulator/serial6*
+fpga/.Xil/
+fpga/bbl.elf.txt
+fpga/vivado_*.str
+fpga/vmlinux.txt

.gitmodules

@@ -1,6 +1,3 @@
-[submodule "riscv-tools"]
-	path = riscv-tools
-	url = https://github.com/riscv/riscv-tools.git
 [submodule "hardfloat"]
 	path = hardfloat
 	url = https://github.com/ucb-bar/berkeley-hardfloat.git
@@ -13,3 +10,6 @@
 [submodule "firrtl"]
 	path = firrtl
 	url = https://github.com/ucb-bar/firrtl.git
+[submodule "src/main/scala/boom"]
+	path = src/main/scala/boom
+	url = https://github.com/shinezyy/BOOM-inside-LvNA.git

.travis.yml

@@ -70,8 +70,8 @@ jobs:
     - &test
       stage: Test
       script:
-        - travis_wait 80 make emulator-ndebug -C regression SUITE=UnittestSuite JVM_MEMORY=3G
-        - travis_wait 80 make emulator-regression-tests -C regression SUITE=UnittestSuite JVM_MEMORY=3G
+        - travis_wait 100 make emulator-ndebug -C regression SUITE=UnittestSuite JVM_MEMORY=3G VERILATOR_THREADS=1
+        - travis_wait 100 make emulator-regression-tests -C regression SUITE=UnittestSuite JVM_MEMORY=3G VERILATOR_THREADS=1
     - <<: *test
       script:
         - travis_wait 80 make emulator-ndebug -C regression SUITE=JtagDtmSuite JVM_MEMORY=3G

bootrom/Makefile

@@ -13,3 +13,4 @@ all: $(bootrom_img)
 
 %.elf: %.S linker.ld
 	$(GCC) -Tlinker.ld $< -nostdlib -static -Wl,--no-gc-sections -o $@
+	riscv64-unknown-elf-objdump -d $@ >bootrom.txt

bootrom/bootrom.S

@@ -1,18 +1,20 @@
+// #define DRAM_BASE 0x80000000
 #define DRAM_BASE 0x100000000
 
 .section .text.start, "ax", @progbits
 .globl _start
 _start:
-  csrwi 0x7c1, 0 // disable chicken bits
+  // csrwi 0x7c1, 0 // disable chicken bits
   li s0, DRAM_BASE
   csrr a0, mhartid
   la a1, _dtb
+
   jr s0
 
 .section .text.hang, "ax", @progbits
 .globl _hang
 _hang:
-  csrwi 0x7c1, 0 // disable chicken bits
+  // csrwi 0x7c1, 0 // disable chicken bits
   csrr a0, mhartid
   la a1, _dtb
   csrwi mie, 0

build.sbt

@@ -16,7 +16,7 @@ lazy val commonSettings = Seq(
   traceLevel   := 15,
   scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"),
   libraryDependencies ++= Seq("org.scala-lang" % "scala-reflect" % scalaVersion.value),
-  libraryDependencies ++= Seq("org.json4s" %% "json4s-jackson" % "3.5.3"),
+  libraryDependencies ++= Seq("org.json4s" %% "json4s-jackson" % "3.6.1"),
   addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full)
 )
 

chisel3

@@ -14,11 +14,13 @@ LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(abspath $(sim_d
 
 emu = emulator-$(PROJECT)-$(CONFIG)
 emu_debug = emulator-$(PROJECT)-$(CONFIG)-debug
+origin_emu = emulator-$(PROJECT)-$(CONFIG)-origin # without init mem
 
 include $(sim_dir)/Makefrag-verilator
 
 all: $(emu)
 debug: $(emu_debug)
+emu_origin: $(origin_emu)
 
 clean:
 	rm -rf *.o *.a emulator-* $(generated_dir) $(generated_dir_debug) DVEfiles $(output_dir)
@@ -33,11 +35,11 @@ ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),)
 -include $(generated_dir)/$(long_name).d
 endif
 
-$(output_dir)/%.run: $(output_dir)/% $(emu)
-	./$(emu) +max-cycles=$(timeout_cycles) $< 2> /dev/null 2> $@ && [ $$PIPESTATUS -eq 0 ]
+$(output_dir)/%.run: $(output_dir)/% $(origin_emu)
+	./$(origin_emu) +max-cycles=$(timeout_cycles) $< 2> /dev/null 2> $@ && [ $$PIPESTATUS -eq 0 ]
 
-$(output_dir)/%.out: $(output_dir)/% $(emu)
-	./$(emu) +max-cycles=$(timeout_cycles) +verbose $< $(disasm) $@ && [ $$PIPESTATUS -eq 0 ]
+$(output_dir)/%.out: $(output_dir)/% $(origin_emu)
+	./$(origin_emu) +max-cycles=$(timeout_cycles) +verbose $< $(disasm) $@ && [ $$PIPESTATUS -eq 0 ]
 
 $(output_dir)/%.vcd: $(output_dir)/% $(emu_debug)
 	./$(emu_debug) +max-cycles=$(timeout_cycles) +verbose -v$@ $< $(disasm) $(patsubst %.vcd,%.out,$@) && [ $$PIPESTATUS -eq 0 ]

emulator/Makefile

@@ -8,7 +8,11 @@ verilog = \
   $(generated_dir)/$(long_name).v \
   $(generated_dir)/$(long_name).behav_srams.v \
 
-.SECONDARY: $(firrtl) $(verilog)
+origin_verilog = \
+  $(generated_dir)/$(long_name).v \
+  $(generated_dir)/$(long_name).origin_behav_srams.v \
+
+.SECONDARY: $(firrtl) $(verilog) $(origin_verilog)
 
 $(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(bootrom_img)
 	mkdir -p $(dir $@)
@@ -24,8 +28,12 @@ $(generated_dir)/$(long_name).behav_srams.v : $(generated_dir)/$(long_name).conf
   $(mem_init) $@.tmp mem_ext bin.txt $(generated_dir)/$(long_name).json > $@
 	rm -f $@.tmp
 
+$(generated_dir)/$(long_name).origin_behav_srams.v : $(generated_dir)/$(long_name).conf $(VLSI_MEM_GEN)
+	cd $(generated_dir) && \
+	$(VLSI_MEM_GEN) $(generated_dir)/$(long_name).conf > $@
+
 # Build and install our own Verilator, to work around versionining issues.
-VERILATOR_VERSION=4.004
+VERILATOR_VERSION=4.008
 VERILATOR_SRCDIR ?= verilator/src/verilator-$(VERILATOR_VERSION)
 VERILATOR_TARGET := $(abspath verilator/install/bin/verilator)
 INSTALLED_VERILATOR ?= $(VERILATOR_TARGET)
@@ -55,13 +63,14 @@ verilator: $(INSTALLED_VERILATOR)
 
 # Run Verilator to produce a fast binary to emulate this circuit.
 VERILATOR := $(INSTALLED_VERILATOR) --cc --exe
+VERILATOR_THREADS ?= 2
 VERILATOR_FLAGS := --top-module $(MODEL) \
   +define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
   +define+RANDOMIZE_GARBAGE_ASSIGN \
   +define+STOP_COND=\$$c\(\"done_reset\"\) --assert \
   --output-split 20000 \
   --output-split-cfuncs 20000 \
-  --threads 4 \
+  --threads $(VERILATOR_THREADS) \
 	-Wno-STMTDLY --x-assign unique \
   -I$(vsrc) \
   -O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -DTEST_HARNESS=V$(MODEL) -include $(csrc)/verilator.h -include $(generated_dir)/$(PROJECT).$(CONFIG).plusArgs"
@@ -84,3 +93,12 @@ $(emu_debug): $(verilog) $(cppfiles) $(headers) $(generated_dir)/$(long_name).d
 	-o $(abspath $(sim_dir))/$@ $(verilog) $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
 	-CFLAGS "-I$(generated_dir_debug) -include $(model_header_debug)"
 	$(MAKE) VM_PARALLEL_BUILDS=1 -C $(generated_dir_debug)/$(long_name) -f V$(MODEL).mk
+
+$(origin_emu): $(origin_verilog) $(cppfiles) $(headers) $(INSTALLED_VERILATOR)
+	mkdir -p $(generated_dir)/$(long_name)
+	$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir)/$(long_name) \
+	-o $(abspath $(sim_dir))/$@ $(origin_verilog) $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
+	-CFLAGS "-I$(generated_dir) -include $(model_header)"
+	$(MAKE) VM_PARALLEL_BUILDS=1 -C $(generated_dir)/$(long_name) -f V$(MODEL).mk
+
+