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SoCMake

Documentation | Examples | API documentation

Introduction

SoCMake is a library for CMake that adds support for hardware development. It bridges the gap between software and hardware build flows, and allows for building complex System-on-Chip projects using a unified build system.

Unlike other hardware build systems, SoCMake reuses the mature CMake infrastructure instead of building it from scratch, benefiting from decades of development that went into CMake.

Features

Comparing to other build systems, SoCMake's biggest strength is first class support for C,C++ compilation and cross-compilation. SoCMake key features are:

  • First class C, C++ compilation support
  • Support for Cross-Compilation of (ARM, RiscV,...) application code.
  • Extensive HDL simulation support (Verilog, SystemVerilog, VHDL)
  • SystemC and SystemC-UVM support
  • Mixed-language SV-VHDL-SC simulation
  • SystemVerilog-UVM and VHDL-UVVM support
  • CocoTB Python co-simulation support
  • Software and IP block package management with CMake package managers
  • HDL code generation and conversion (PeakRDL, desyrdl, yosys, sv2v, ..)
  • Build graph generation with graphviz

Getting started

SoCMake is lightweight and has minimal dependencies. The only mandatory dependencies are CMake>=3.27.0 and make or/and ninja (Install Dependencies)

One-Time Bootstrap Installation (Recommended)

Install the SoCMake bootstrap files once on your system:

curl -fsSL https://raw.githubusercontent.com/HEP-SoC/SoCMake/master/bootstrap/bootstrap.sh | sh

This installs bootstrap files to ~/.local/lib/cmake/socmake that automatically fetches the correct SoCMake version for each project. In order to use it create a file called CMakeLists.txt

cmake_minimum_required(VERSION 3.27) # CMake minimum required version
project(adder NONE)                  # Name of CMake project

find_package(socmake REQUIRED)

# Create an IP block called adder
add_ip(adder)
# Add verilog file adder.v to adder IP
ip_sources(adder VERILOG
                 ./adder.v)
# Create a target for Icarus Verilog
iverilog(adder)

The directory structure should be as following:

adder/
├── adder.v
└── CMakeLists.txt

In order to run the simulation execute the following:

mkdir build && cd build
cmake ../
make run_adder_iverilog

The following message should be printed:

[ 50%] Compile adder with iverilog
[ 50%] Built target adder_iverilog
[100%] Run iverilog testbench compiled from adder
Hello from Adder!
[100%] Built target run_adder_iverilog

Examples

For more examples on how to use SoCMake including the previous example visit Examples. Some of the examples include:

  • Simple Verilog and VHDL testbenches
  • Mixed language simulation examples SystemVerilog-VHDL, SystemC-SystemVerilog
  • UVM-SystemC and SystemC examples
  • Verilator C++ and SystemC teshbench
  • Foreign Language Interfaces such as DPI-C, VHPIDirect

Additionally some more complex examples are available on separate repositories:

Check out the Documentation

Check out the Pipeline Status (CDash)