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Update comgr_utils for October 2025 RDTS release.
1 parent 35fbf01 commit 2b35675

3 files changed

Lines changed: 87 additions & 3 deletions

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CMakeLists.txt

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@@ -1,3 +1,8 @@
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#######################################################################################################################
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### Copyright (c) 2018-2025 Advanced Micro Devices, Inc. All rights reserved.
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### @author AMD Developer Tools Team
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#######################################################################################################################
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cmake_minimum_required (VERSION 3.5.1)
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project (ComgrUtils)
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source/comgr_utils.cpp

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@@ -125,6 +125,15 @@ namespace amdt
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const char* kPalMdTagUserDataRegMap = ".user_data_reg_map";
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const char* kPalMdTagUsesCps = ".uses_cps";
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const char* kPalMdTagThreadGroupDimensions = ".threadgroup_dimensions";
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const char* kPalMdTagComputeRegisters = ".compute_registers";
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const char* kPalMdTagDynamicVgprEn = ".dynamic_vgpr_en";
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const char* kPalMdTagTgSizeEn = ".tg_size_en";
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const char* kPalMdTagTgidXEn = ".tgid_x_en";
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const char* kPalMdTagTgidYEn = ".tgid_y_en";
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const char* kPalMdTagTgidZEn = ".tgid_z_en";
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const char* kPalMdTagTidigCompCnt = ".tidig_comp_cnt";
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const char* kPalMdTagXInterleave = ".x_interleave";
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const char* kPalMdTagYInterleave = ".y_interleave";
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// Graphics register metadata.
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const char* kPalMdTagGraphicsRegisters = ".graphics_registers";
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const char* kPalMdTagAaCoverageToShaderSelect = ".aa_coverage_to_shader_select";
@@ -804,6 +813,8 @@ namespace amdt
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}
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}
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ExtractPalMDComputeRegisters(*pipeline_data, ppln);
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// Uses CPS (Continuation Passing Shader).
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MDNode uses_cps = ppln[kPalMdTagUsesCps];
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if (uses_cps.IsValid())
@@ -2074,6 +2085,53 @@ namespace amdt
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return true;
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}
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bool CodeObj::ExtractPalMDComputeRegisters(Pipeline &md_pipeline_data, MDNode &ppln)
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{
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MDNode compute_registers = ppln[kPalMdTagComputeRegisters];
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auto &compute_registers_info = md_pipeline_data.compute_registers_info;
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if (!compute_registers.IsValid())
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{
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ReportInvalidRequiredPalMDMapItem(compute_registers);
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return false;
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}
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MDNode dynamic_vgpr_en = compute_registers[kPalMdTagDynamicVgprEn];
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compute_registers_info.dynamic_vgpr_en = dynamic_vgpr_en.value<bool>();
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dynamic_vgpr_en.Destroy();
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MDNode tg_size_en = compute_registers[kPalMdTagTgSizeEn];
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compute_registers_info.tg_size_en = tg_size_en.value<bool>();
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tg_size_en.Destroy();
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MDNode tgid_x_en = compute_registers[kPalMdTagTgidXEn];
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compute_registers_info.tgid_x_en = tgid_x_en.value<bool>();
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tgid_x_en.Destroy();
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MDNode tgid_y_en = compute_registers[kPalMdTagTgidYEn];
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compute_registers_info.tgid_y_en = tgid_y_en.value<bool>();
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tgid_y_en.Destroy();
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MDNode tgid_z_en = compute_registers[kPalMdTagTgidZEn];
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compute_registers_info.tgid_z_en = tgid_z_en.value<bool>();
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tgid_z_en.Destroy();
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MDNode tidig_comp_cnt = compute_registers[kPalMdTagTidigCompCnt];
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compute_registers_info.tidig_comp_cnt = tidig_comp_cnt.value<uint32_t>();
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tidig_comp_cnt.Destroy();
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MDNode x_interleave = compute_registers[kPalMdTagXInterleave];
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compute_registers_info.x_interleave = x_interleave.value<uint32_t>();
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x_interleave.Destroy();
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MDNode y_interleave = compute_registers[kPalMdTagYInterleave];
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compute_registers_info.y_interleave = y_interleave.value<uint32_t>();
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y_interleave.Destroy();
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compute_registers.Destroy();
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return true;
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}
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bool CodeObj::ExtractPalMdGraphicsRegisterInfo(Pipeline& md_pipeline_data, MDNode& pp_in)
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{
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MDNode graphics_registers = pp_in[kPalMdTagGraphicsRegisters];

source/comgr_utils.h

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@@ -149,7 +149,7 @@ namespace amdt
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{
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#ifdef COMGR_DYNAMIC_LINKING
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#ifdef _WIN32
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module_ = LoadLibrary(_T("amd_comgr_2.dll"));
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module_ = LoadLibrary(_T("amd_comgr_3.dll"));
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#elif defined(__APPLE__)
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module_ = dlopen("libamd_comgr.1.dylib", RTLD_LAZY);
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#else
@@ -987,7 +987,20 @@ namespace amdt
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kComgrUtilsRaw, ///< Output the scan converter's internal mask, unchanged.
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};
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/// Abstracted graphics-only register values.
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/// @brief Abstracted compute-only register values.
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struct ComputeRegistersInfo
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{
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bool dynamic_vgpr_en; ///< Flag indicating if dynamic VGPR allocation is enabled.
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bool tg_size_en;
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bool tgid_x_en;
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bool tgid_y_en;
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bool tgid_z_en;
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uint32_t tidig_comp_cnt;
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uint32_t x_interleave;
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uint32_t y_interleave;
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};
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/// @brief Abstracted graphics-only register values.
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struct GraphicsRegisterInfo
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{
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/// How many LS VGPR components to load.
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HWStageInfo* stage_list; ///< Stage list.
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RegisterData* register_data_list; ///< Register data list.
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ShaderFunctionInfo* shader_function_list; ///< Shader function list.
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GraphicsRegisterInfo graphics_register_info; ///< graphics register info.
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GraphicsRegisterInfo graphics_register_info; ///< Graphics register info.
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ComputeRegistersInfo compute_registers_info; ///< Compute register info.
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};
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/// @brief HSA kernel arguments info.
@@ -1678,6 +1692,13 @@ namespace amdt
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/// @return true if successful, false otherwise.
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bool ExtractPalMDRegisterInfo(Pipeline& md_pipeline_data, MDNode& pp_in);
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/// @brief Helper function for extracting PAL metadata for compute register info.
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///
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/// @param [in] md_pipeline_data The pipeline data.
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/// @param [in] pp_in The metadata node.
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/// @return true if successful, false otherwise.
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bool ExtractPalMDComputeRegisters(Pipeline& md_pipeline_data, MDNode& pp_in);
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/// @brief Helper function for extracting PAL metadata for graphics register info.
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///
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/// @param [in] md_pipeline_data The pipeline data.

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