Merge pull request #113 from zapta/main

Updated examples

Author: zapta

examples/alhambra-ii/bcd-counter/.main_tb.v.swp

@@ -2,34 +2,52 @@
 //-- Using PLL for 48Mhz clock.
 //------------------------------------------------------------------
 
-module main (
-    input  ext_clk,  // 12MHz clock
-    output LED       // LED to blink
+module main #(
+    parameter integer DIV = 8_000_000
+) (
+    input      ext_clk,  // 12MHz clock
+    output reg LED       // LED to blink
 );
 
-  // PLL 12Mhz -> 28Mhz
+  // PLL 12Mhz -> 48Mhz
   //
   // Generated with:
   //   apio raw -- icepll -i 12 -o 48 -q -m -f pll.v
   //   apio format pll.v
   //
   // (See pll.v for additional args that were added manually)
 
+  // 48 Mhz clock from the pll.
   wire sys_clk;
 
+  // Generates the main clock .
   pll pll (
-      .clock_in(ext_clk),
-      .clock_out(sys_clk),
+      .clock_in(ext_clk),  // In 12 Mhz
+      .clock_out(sys_clk),  // Out 48 Mhz
       .locked()
   );
 
-  reg [23:0] counter = 0;
+  reg initialized = 1'b0;
+
+  reg [31:0] counter;
+
+  always @(posedge sys_clk) begin
+    if (!initialized) begin
+      // One time initialization.
+      initialized <= 1'b1;
+      LED <= 1'b1;
+      counter <= 0;
+    end else if (counter >= (DIV - 1)) begin
+      // Delay reached, flip LED and and reset counter.
+      LED <= !LED;
+      counter <= 0;
+    end else begin
+      // Incrementing the delay counter.
+      counter <= counter + 1;
+    end
+  end
 
-  always @(posedge sys_clk) counter <= counter + 1;
 
-  // Should blink at about 2.82Hz
-  // 48M / 2^24 = 2.82
-  assign LED = counter[23];
 
 endmodule
 

examples/alhambra-ii/pll/main.v

@@ -0,0 +1,36 @@
+[*]
+[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
+[*] Wed Jan 28 17:32:05 2026
+[*]
+[dumpfile] "/Volumes/projects/apio-examples-dev/repo/examples/alhambra-ii/pll/_build/default/main_tb.vcd"
+[dumpfile_mtime] "Wed Jan 28 17:30:44 2026"
+[dumpfile_size] 1283
+[savefile] "/Volumes/projects/apio-examples-dev/repo/examples/alhambra-ii/pll/main_tb.gtkw"
+[timestart] 0
+[size] 1000 600
+[pos] -1 -1
+*-15.913198 71800 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] main_tb.
+[treeopen] main_tb.main.
+[sst_width] 253
+[signals_width] 136
+[sst_expanded] 1
+[sst_vpaned_height] 158
+@28
+main_tb.ext_clk
+main_tb.main.sys_clk
+@200
+-
+@28
+main_tb.main.initialized
+@200
+-
+@24
+main_tb.main.counter[31:0]
+@200
+-
+@29
+[color] 2
+main_tb.LED
+[pattern_trace] 1
+[pattern_trace] 0

examples/alhambra-ii/pll/main_tb.gtkw

@@ -0,0 +1,33 @@
+`timescale 1ns / 1ps
+
+module main_tb;
+
+  // Inputs
+  reg  ext_clk = 0;
+
+  // Outputs
+  wire LED;
+
+  // Instantiate the Unit Under Test (UUT)
+  main #(
+      .DIV(4)  // Reduced for faster simulation.
+  ) main (
+      .ext_clk(ext_clk),
+      .LED(LED)
+  );
+
+  // Continious clock
+  always #5 ext_clk = ~ext_clk;
+
+  initial begin
+    // Dump signals to Apio specified .vcd file.
+    $dumpvars(0, main_tb);
+
+    // Run for 20 full clock cycles
+    repeat (20) @(posedge ext_clk);
+
+    // Finish simulation
+    $finish;
+  end
+
+endmodule

examples/alhambra-ii/pll/main_tb.v

@@ -16,6 +16,10 @@ module pll (
     output locked
 );
 
+`ifdef SYNTHESIS
+
+  // Real implemenation using a primitive cell for synthesis.
+
   SB_PLL40_CORE #(
       .FEEDBACK_PATH("SIMPLE"),
       .DIVR(4'b0000),  // DIVR =  0
@@ -39,4 +43,13 @@ module pll (
       .DYNAMICDELAY()
   );
 
+`else
+
+  // Fake implementation for simulation
+
+  assign clock_out = clock_in;
+  assign locked = 1'b1;
+
+`endif
+
 endmodule

examples/alhambra-ii/pll/pll.v

@@ -4,10 +4,10 @@
 // See examples here https://github.com/sipeed/TangNano-20K-example
 
 IO_LOC "sys_clk"  4;
-IO_PORT "sys_clk" PULL_MODE=UP BANK_VCCIO=1.8;;
+IO_PORT "sys_clk" PULL_MODE=UP IO_TYPE=LVCMOS33 BANK_VCCIO=3.3;
 
 IO_LOC "led"      15; // Active low
-IO_PORT "led" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
+IO_PORT "led"     PULL_MODE=UP DRIVE=8 IO_TYPE=LVCMOS33 BANK_VCCIO=3.3;
 
 // Per https://github.com/YosysHQ/nextpnr/issues/1515
 CLOCK_LOC "sys_clk" BUFG;

examples/sipeed-tang-nano-20k/blinky/blinky.cst

@@ -4,10 +4,10 @@
 // See examples here https://github.com/sipeed/TangNano-20K-example
 
 IO_LOC "CLK"  4;
-IO_PORT "CLK" PULL_MODE=UP BANK_VCCIO=1.8;;
+IO_PORT "clk" PULL_MODE=UP IO_TYPE=LVCMOS33;
 
 IO_LOC "LED"  15; // Active low
-IO_PORT "LED" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
+IO_PORT "led" PULL_MODE=UP DRIVE=8 IO_TYPE=LVCMOS33;
 
 // Per https://github.com/YosysHQ/nextpnr/issues/1515
 CLOCK_LOC "CLK" BUFG;

examples/sipeed-tang-nano-20k/speed-test/pinout.cst

@@ -118,6 +118,7 @@ def test_example_env(
 
     run_cmd(["apio", "build", "-e", env_name])
     run_cmd(["apio", "lint", "-e", env_name])
+    run_cmd(["apio", "lint", "--nosynth", "-e", env_name])
     run_cmd(["apio", "graph", "-n", "-e", env_name])
     run_cmd(["apio", "report", "-e", env_name])
 
@@ -128,6 +129,10 @@ def test_example_env(
         for testbench in testbenches:
             test_testbench_output(env_name, testbench)
 
+    # -- Test 'apio test --default'
+    if testbenches:
+        run_cmd(["apio", "test", "--default", "-e", env_name])
+
     # -- Test 'apio sim' (default testbench)
     if testbenches:
         run_cmd(["apio", "clean"])